MC68HC08AZ0 Datasheet, PDF (177/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
External Interrupt Module (IRQ)
Functional description
IRQ pin
A ‘0’ on the IRQ pin can latch an interrupt request into the IRQ latch. A
vector fetch, software clear, or reset clears the IRQ latch.
If the MODE1 bit is set, the IRQ pin is both falling-edge-sensitive and
low-level-sensitive. With MODE1 set, both of the following actions must
occur to clear the IRQ latch:
• Vector fetch or software clear — a vector fetch generates an
interrupt acknowledge signal to clear the latch. Software may
generate the interrupt acknowledge signal by writing a ‘1’ to the
ACK1 bit in the interrupt status and control register (ISCR). The
ACK1 bit is useful in applications that poll the IRQ pin and require
software to clear the IRQ latch. Writing to the ACK1 bit can also
prevent spurious interrupts due to noise. Setting ACK1 does not
affect subsequent transitions on the IRQ pin. A falling edge that
occurs after writing to the ACK1 bit latches another interrupt
request. If the IRQ mask bit, IMASK1, is clear, the CPU loads the
program counter with the vector address at locations $FFFA and
$FFFB.
• Return of the IRQ pin to ‘1’ — as long as the IRQ pin is at ‘0’, the
IRQ latch remains set.
The vector fetch or software clear and the return of the IRQ pin to ‘1’ may
occur in any order. The interrupt request remains pending as long as the
IRQ pin is at ‘0’. A reset will clear the latch and the MODEx control bit,
thereby clearing the interrupt even if the pin stays low.
If the MODE1 bit is clear, the IRQ pin is falling-edge-sensitive only. With
MODE1 clear, a vector fetch or software clear immediately clears the
IRQ latch.
The IRQF bit in the ISCR register can be used to check for pending
interrupts. The IRQF bit is not affected by the IMASK1 bit, which makes
it useful in applications where polling is preferred.
The BIH or BIL instruction is used to read the logic level on the IRQ pin.
NOTE: When using the level-sensitive interrupt trigger, false interrupts can be
avoided by masking interrupt requests in the interrupt routine.
5-irq
MOTOROLA
External Interrupt Module (IRQ)
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MC68HC08AZ0
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