MC68HC08AZ0 Datasheet, PDF (236/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Serial Peripheral Interface Module (SPI)
NOTE:
A ‘1’ on the SS pin of a slave SPI puts the MISO pin in a high impedance
state. Also, the slave SPI ignores all incoming SPSCK clocks, even if it
was already in the middle of a transmission.
To clear the MODF flag, the SPSCR should be read with the MODF bit
set and then the SPCR register should be written to. This entire clearing
mechanism must occur with no MODF condition existing or else the flag
will not be cleared.
Interrupts
Four SPI status flags can be enabled to generate CPU interrupt
requests:
Table 3. SPI interrupts
Flag
SPTE (Transmitter Empty)
SPRF (Receiver Full)
OVRF (Overflow)
MODF (Mode Fault)
Request
SPI Transmitter CPU Interrupt Request (SPTIE = 1)
SPI Receiver CPU Interrupt Request (SPRIE = 1)
SPI Receiver/Error Interrupt Request (SPRIE = 1, ERRIE = 1)
SPI Receiver/Error Interrupt Request (SPRIE = 1, ERRIE = 1, MODFEN = ‘1’)
The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag
to generate transmitter CPU interrupt requests.
The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to
generate receiver CPU interrupt requests, provided that the SPI is
enabled (SPE = 1).
The error interrupt enable bit (ERRIE) enables both the MODF and
OVRF flags to generate a receiver/error CPU interrupt request.
The mode fault enable bit (MODFEN) can prevent the MODF flag from
being set so that only the OVRF flag is enabled to generate
receiver/error CPU interrupt requests.
MC68HC08AZ0
234
Serial Peripheral Interface Module (SPI)
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