MC68HC08AZ0 Datasheet, PDF (89/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
System Integration Module (SIM)
Introduction
STOP/WAIT
CONTROL
SIM
COUNTER
÷2
CLOCK
CONTROL
CLOCK GENERATORS
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO CGM)
COP CLOCK
CGMXCLK (FROM CGM)
CGMOUT (FROM CGM)
INTERNAL CLOCKS
RESET
PIN LOGIC
POR CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
MASTER
RESET
CONTROL
RESET
LVI (FROM LVI MODULE)
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP (FROM COP MODULE)
INTERRUPT CONTROL
AND PRIORITY DECODE
INTERRUPT SOURCES
CPU INTERFACE
Figure 1. SIM block diagram
Table 1. SIM I/O register summary
Register Name
Bit 7 6
5
4
3
SIM Break Status Register (SBSR) R
R
R
R
R
SIM Reset Status Register (SRSR) POR PIN COP ILOP ILAD
SIM Break Flag Control Register (SBFCR) BCFE 0
0
0
0
R = Reserved for factory test
2
1 Bit 0 Addr.
R SBSW R $FE00
0
LVI 0 $FE01
0
0
0 $FE03
Table 2 shows the internal signal names used in this section.
3-sim
MOTOROLA
System Integration Module (SIM)
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MC68HC08AZ0
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