MC68HC08AZ0 Datasheet, PDF (288/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Timer Interface Module B (TIMB)
NOTE:
c. Write 1:0 (to clear output on compare) or 1:1 (to set
output on compare) to the edge/level select bits,
ELSxB:ELSxA. The output action on compare must
force the output to the complement of the pulse width
level. (See Table 1)
In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to
self-correct in the event of software error or noise. Toggling on output
compare can also cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
5. In the TIMB status control register (TBSC), clear the TIMB
stop bit, TSTOP.
Setting MS0B links channels 0 and 1 and configures them for buffered
PWM operation. The TIMB channel 0 registers (TBCH0H:TBCH0L)
initially control the buffered PWM output. TIMB status control register 0
(TBSCR0) controls and monitors the PWM signal from the linked
channels. MS0B Takes priority over MS0A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on
TIMB overflows. Subsequent output compares try to force the output to
a state it is already in and have no effect. The result is a 0% duty cycle
output.
Setting the channel x maximum duty cycle bit (CHxMAX) and clearing
the TOVx bit generates a 100% duty cycle output. See TIMB channel
status and control registers (TBSC0–TBSC1) on page 294.
MC68HC08AZ0
286
Timer Interface Module B (TIMB)
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