MC68HC08AZ0 Datasheet, PDF (431/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Index
SCI . . . . . . . . . . . . . . . . . . . .185, 203, 208
SPI . . . . . . . . . . . . . . . . . . . . . . . .235, 246
DMARE bit (SCI DMA receive enable bit) 194,
206, 209
DMATE bit (SCI DMA transfer enable bit)187,
207–208
E
EEACR
EEPROM array configuration register . .64
EECR
EEPROM control register. . . . . . . . . . . .62
EENVR
EEPROM non-volatile register . . . . . . . .64
EEPROM. . . . . . . . . . . . . . . . . . . . . . . .56–65
block protection . . . . . . . . . . . . . . . . . . .60
configuration . . . . . . . . . . . . . . . . . . . . .60
EEACR. . . . . . . . . . . . . . . . . . . . . . . . . .64
EECR . . . . . . . . . . . . . . . . . . . . . . . . . . .62
EENVR. . . . . . . . . . . . . . . . . . . . . . . . . .64
erasing . . . . . . . . . . . . . . . . . . . . . . . . . .58
programming . . . . . . . . . . . . . . . . . . . . .57
size. . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
EESEC
MORB . . . . . . . . . . . . . . . . . . . . . . . . .138
electrostatic damage . . . . . . . . . . . . . . . . .328
ELSxA/B bits (TIM edge/level select bits) 272,
296
ENSCI bit (enable SCI bit). . . . . . . . .185, 200
EPROM/OTPROM security . . . . . . . . . . . .137
external crystal . . . . . . . . . . . . . . . . . . . . .103
external filter capacitor . . . . . . . . . . .118, 131
external filter capacitor pin (CGMXFC) . . .118
external pin reset. . . . . . . . . . . . . . . . . . . . .90
F
f_BUS (bus frequency). . . . . . . . . . . . . . . . . .115
FE bit (SCI framing error bit) . . . . . . . . . . .195
FE bit (SCI receiver framing error bit) . . . .211
FEIE bit (SCI framing error interrupt enable bit)
195
FEIE bit (SCI receiver framing error interrupt
enable bit). . . . . . . . . . . . . . . . . . . .207
flag protection in break mode . . . . . . . . . . 100
f_NOM (nominal center-of-range frequency) . 112
f_rclk (PLL reference clock frequency). . . . . 115
f_RCLK (PLL reference clock frequency) . . . . 112
f_RDV (PLL final reference frequency) . . . . . 112
functional operating range . . . . . . . . . . . . 399
f_VCLK (VCO output frequency) . . . . . . . . . . 112
f_VRS (VCO programmed center-of-range fre-
quency) . . . . . . . . . . . . .112, 115, 126
H
H bit
CCR. . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
I
I bit
CCR. . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
I bit (interrupt mask) . . . . . . . . . . . . . 173, 177
I/O port register summary . . . . . . . . . . . . . 328
I/O registers
locations . . . . . . . . . . . . . . . . . . . . . . . . 24
IAB (internal address bus) . . . . . . . . . . . . 140
IBUS . . . . . . . . . . . . . . . . . . . . . . . . . . . 89, 95
IDLE bit (SCI receiver idle bit). . . . . . 194, 209
idle character . . . . . . . . . . . . . . . . . . . . . . 187
ILAD
SRSR. . . . . . . . . . . . . . . . . . . . . . . . . . 106
ILIE bit (SCI idle line interrupt enable bit) 194,
204
ILOP
SRSR. . . . . . . . . . . . . . . . . . . . . . . . . . 106
ILOP bit (illegal opcode reset bit) . . . . . . . 106
ILTY bit (SCI idle line type bit) . . . . . . . . . 201
IMASK1 bit (IRQ interrupt mask bit) . 173, 177
IMASKK
Keyboard interrupt mask bit. . . . . . . . . 324
index register (H:X) . . . . . . . . . . . . . . . . 70, 98
input capture . . . . . . . . . . . . . . .256, 281, 298
interrupt
external interrupt pin (IRQ) . . . . . . . . . . 15
interrupt status and control register (ISCR) . .
172
interrupts
MOTOROLA
Index
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