MC68HC08AZ0 Datasheet, PDF (339/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
I/O Ports
Port D
Port D
Port D is an 8-bit general-purpose I/O port.
Port D data register Port D is an 8-bit special function port that shares seven of it’s pins with
(PTD)
the analog to digital converter and two with the TIMA and TIMB modules.
Bit 7
6
5
4
3
2
PTD
$0003
Read:
PTD7
Write:
PTD6
PTD5
PTD4
PTD3
PTD2
Reset:
Unaffected by reset
Alternate
Functions
R
TACLK
TBCLK
Figure 10. Port D data register (PTD)
1
PTD1
Bit 0
PTD0
PTD[7:0] — Port D data bits
PTD[7:0] are read/write, software programmable bits. Data direction
of PTD[7:0] pins are under the control of the corresponding bit in data
direction register D.
Data direction register D determines whether each port D pin is an
input or an output. Writing a logic one to a DDRD bit enables the
output buffer for the corresponding port D pin; a logic zero disables
the output buffer
NOTE:
Data direction register D (DDRD) does not affect the data direction of
port D pins that are being used by the TIMA or TIMB. However, the
DDRD bits always determine whether reading port D returns the states
of the latches to logic 0.
TACLK/TBCLK — Timer clock input
The PTD6/TACLK pin is the external clock input for the TIMA. The
PTD4/TBCLK pin is the external clock input for the TIMB. The
prescaler select bits, PS[2:0], select PTD6/TACLK or PTD4/TBCLK
as the TIM clock input (see TIMA channel status and control registers
(TASC0–TASC3) on page 270 and TIMB status and control register
11-io
MOTOROLA
I/O Ports
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MC68HC08AZ0
337