MC68HC08AZ0 Datasheet, PDF (135/444 Pages) Motorola, Inc – Advance Information

Reaction time
calculation
27-cgm
MOTOROLA
Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
Acquisition/lock time specifications
PLL may become unstable. Also, always choose a capacitor with a tight
tolerance (±20% or better) and low dissipation.
The actual acquisition and lock times can be calculated using the
equations below. These equations yield nominal values under the
following conditions:
• Correct selection of filter capacitor, C_F, (see Choosing a filter
capacitor on page 132)
• Room temperature operation
• Negligible external leakage on CGMXFC
• Negligible noise
The K factor in the equations is derived from internal PLL parameters.
K_ACQ is the K factor when the PLL is configured in acquisition mode, and
K_TRK is the K factor when the PLL is configured in tracking mode. See
Acquisition and tracking modes on page 113.
t_ACQ
=



V--f--_{R-D---D-D---V-A--}


K-----_A^--8--_C^----_Q^{--}
t_AL
=



V--f--_{R-D---D-D---V-A--}


-K----_R--4--_T---_K--_
t_LOCK = t_ACQ + t_AL
Note the inverse proportionality between the lock time and the reference
frequency.
In automatic bandwidth control mode the acquisition and lock times are
quantized into units based on the reference frequency. <blue>See
Manual and automatic PLL bandwidth modes. A certain number of clock
cycles, n_ACQ, is required to ascertain whether the PLL is within the
tracking mode entry tolerance ∆_TRK, before exiting acquisition mode.
Also, a certain number of clock cycles, n_TRK, is required to ascertain
whether the PLL is within the lock mode entry tolerance ∆_LOCK.
Therefore, the acquisition time t_ACQ, is an integer multiple of n_ACQ/f_RDV,
Clock Generator Module (CGM)
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MC68HC08AZ0
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