MC68HC08AZ0 Datasheet, PDF (208/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Serial Communications Interface Module (SCI)
SCC3
$0015
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
R8
T8 DMARE DMATE ORIE NEIE FEIE
U
U
0
0
0
0
0
= Unimplemented
U = Unaffected
R = Reserved
Figure 7. SCI control register 3 (SCC3)
Bit 0
PEIE
0
R8 — Received bit 8
When the SCI is receiving 9-bit characters, R8 is the read-only ninth
bit (bit 8) of the received character. R8 is received at the same time
that the SCDR receives the other 8 bits.
When the SCI is receiving 8-bit characters, R8 is a copy of the eighth
bit (bit 7). Reset has no effect on the R8 bit.
T8 — Transmitted bit 8
When the SCI is transmitting 9-bit characters, T8 is the read/write
ninth bit (bit 8) of the transmitted character. T8 is loaded into the
transmit shift register at the same time that the SCDR is loaded into
the transmit shift register. Reset has no effect on the T8 bit.
DMARE — DMA receive enable bit
This read/write bit enables the DMA to service SCI receiver DMA
service requests generated by the SCRF bit. (See 14.7.4.) Setting the
DMARE bit disables SCI receiver CPU interrupt requests. Reset
clears the DMARE bit.
1 = DMA enabled to service SCI receiver DMA service requests
generated by the SCRF bit
(SCI receiver CPU interrupt requests disabled)
0 = DMA not enabled to service SCI receiver DMA service requests
generated by the SCRF bit
(SCI receiver CPU interrupt requests enabled)
MC68HC08AZ0
206
Serial Communications Interface Module (SCI)
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28-sci
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