MC68HC08AZ0 Datasheet, PDF (32/444 Pages) Motorola, Inc – Advance Information

Memory Map
Freescale Semiconductor, Inc.
Addr.
Name
$0042
TimerB Counter Register R:
Low (TBCNTL) W:
$0043
TimerB Modulo Register R:
High (TBMODH) W:
$0044
TimerB Modulo Register R:
Low (TBMODL) W:
Timer B Channel 0Status R:
$0045
and Control Register
(TBSC0) ^W:
$0046
Timer B Channel 0Register
High (TBCH0H)
R:
W:
$0047
Timer B Channel 0Register
Low (TBCH0L)
R:
W:
$0048
Timer B Channel 1Status/ R:
Control Register (TBSC1) W:
$0049
Timer B Channel 1Register
High (TBCH1H)
R:
W:
$004A
Timer B Channel1Register R:
Low (TBCH1L) W:
Programmable Interrupt R:
$004B
Timer Status & Control
Register (PSC) ^W:
$004C
PIT Counter Register R:
HIGH) (PCNTH) W:
$004D
PIT Counter Register Low R:
(PCNTL) W
$004E
PIT Modulo Register High R
(PMODH) W
$004F
PIT Modulo Register Low R:
(PMODL) W
Bit 7
Bit 7
Bit 15
Bit 7
CH4F
0
Bit 15
Bit 7
CH5F
0
Bit 15
Bit 7
POF
0
Bit 15
7
Bit 15
7
6
6
14
6
CH4IE
14
6
CH5IE
14
6
PIE
14
6
14
6
5
5
13
5
MS4B
13
5
MS5B
13
5
PSTOP
13
5
13
5
4
4
12
4
MS4A
12
4
MS5A
12
4
0
PRST
12
4
12
4
3
2
1
Bit 0
3
2
1
0
11
10
3
2
9
Bit 8
1
Bit 0
ELS4B ELS4A TOV4 CH0MAX
11
10
9
8
3
2
1
0
ELS5B ELS5A TOV5 CH1MAX
11
10
9
8
3
2
1
0
0
PPS2 PPS1 PPS0
11
10
9
8
3
2
1
0
11
10
9
8
3
2
1
0
$FE00
SIM Break Status Register R:
(SBSR) W:
R
R
$FE01
SIM Reset Status Register R:
(SRSR) W:
POR
PIN
R
COP
R
ILOP
R
ILAD
R
SBSW
R
0
LVI
0
$FE03
SIM Break Flag Control R:
Register (SBFCR) W:
BCFE
R
R
R
R
R
R
R
$FE07
Reserved ^R:
W:
$FE0C
Break Address Register R:
High (BRKH) W:
Bit 15
14
13
$FE0D
Break Address Register R:
Low (BRKL) W:
Bit 7
6
5
12
11
10
4
3
2
9
Bit 8
1
Bit 0
= Unimplemented
R = Reserved
Figure 5. Control, status, and data registers (Sheet 4 of 5)
MC68HC08AZ0
30
Memory Map
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