MC68HC08AZ0 Datasheet, PDF (210/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Serial Communications Interface Module (SCI)
SCI status register
1 (SCS1)
SCI status register 1 contains flags to signal the following conditions:
• Transfer of SCDR data to transmit shift register complete
• Transmission complete
• Transfer of receive shift register data to SCDR complete
• Receiver input idle
• Receiver overrun
• Noisy data
• Framing error
• Parity error
Bit 7
6
5
4
3
2
SCS1 ^{Read: SCTE}
TC
SCRF IDLE
OR
NF
$0016 _Write:
Reset: 1
1
0
0
0
0
= Unimplemented
Figure 8. SCI status register 1 (SCS1)
1
Bit 0
FE
PE
0
0
SCTE — SCI transmitter empty bit
This clearable, read-only bit is set when the SCDR transfers a
character to the transmit shift register. SCTE can generate an SCI
transmitter CPU interrupt request or an SCI transmitter DMA service
request. When the SCTIE bit in SCC2 is set and the DMATE bit in
SCC3 is clear, SCTE generates an SCI transmitter CPU interrupt
request. With both the SCTIE and DMATE bits set, SCTE generates
an SCI transmitter DMA service request. In normal operation, clear
the SCTE bit by reading SCS1 with SCTE set and then writing to
SCDR. In DMA transfers, the DMA automatically clears the SCTE bit
when it writes to the SCDR. Reset sets the SCTE bit.
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
NOTE: Setting the TE bit for the first time also sets the SCTE bit. When enabling
SCI transmitter DMA service requests, set the TE bit after setting the
MC68HC08AZ0
208
Serial Communications Interface Module (SCI)
For More Information On This Product,
Go to: www.freescale.com
30-sci
MOTOROLA