MC68HC08AZ0 Datasheet, PDF (224/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Serial Peripheral Interface Module (SPI)
Master mode
The SPI operates in master mode when the SPI master bit, SPMSTR, is
set.
NOTE:
The SPI modules should be configured as master and slave before they
are enabled. Also, the master SPI should be enabled before the slave
SPI. Similarly, Disable the slave SPI should be disabled before disabling
the master SPI. See SPI control register (SPCR) on page 243.
Only a master SPI module can initiate transmissions. Software begins
the transmission from a master SPI module by writing to the SPI data
register. If the shift register is empty, the byte immediately transfers to
the shift register, setting the SPI transmitter empty bit, SPTE. The byte
begins shifting out on the MOSI pin under the control of the serial clock.
See Figure 3.
The SPR1 and SPR0 bits control the baud rate generator and determine
the speed of the shift register. See SPI status and control register
(SPSCR) on page 246. Through the SPSCK pin, the baud rate generator
of the master also controls the shift register of the slave peripheral.
As the byte shifts out on the MOSI pin of the master, another byte shifts
in from the slave on the master’s MISO pin. The transmission ends when
the receiver full bit, SPRF, becomes set. At the same time that SPRF
becomes set, the byte from the slave transfers to the receive data
register. In normal operation, SPRF signals the end of a transmission.
Software clears SPRF by reading the SPI status and control register with
MC68HC08AZ0
222
Serial Peripheral Interface Module (SPI)
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