MC68HC08AZ0 Datasheet, PDF (234/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Serial Peripheral Interface Module (SPI)
BYTE 1
SPI RECEIVE 1
COMPLETE
SPRF
BYTE 2
5
BYTE 3
7
BYTE 4
11
OVRF
READ SPSCR
2
4
6
9
12
14
READ SPDR
3
8
10
13
1 BYTE 1 SETS SPRF BIT.
8 CPU READS BYTE 2 IN SPDR,
2 CPU READS SPSCR WITH SPRF BIT SET
CLEARING SPRF BIT.
AND OVRF BIT CLEAR.
9 CPU READS SPSCR AGAIN
3 CPU READS BYTE 1 IN SPDR,
TO CHECK OVRF BIT.
CLEARING SPRF BIT.
10 CPU READS BYTE 2 SPDR,
4 CPU READS SPSCR AGAIN
CLEARING OVRF BIT.
TO CHECK OVRF BIT.
11 BYTE 4 SETS SPRF BIT.
5 BYTE 2 SETS SPRF BIT.
12 CPU READS SPSCR.
6
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
13 ^{CPU READS BYTE 4 IN SPDR,}
CLEARING SPRF BIT.
7 BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST. _{14 CPU READS SPSCR AGAIN}
TO CHECK OVRF BIT.
Figure 9. Clearing SPRF when OVRF interrupt is not enabled
Mode fault error
For the MODF flag to be set, the mode fault error enable bit (MODFEN)
must be set. Clearing the MODFEN bit does not clear the MODF flag but
does prevent MODF from being set again after MODF is cleared.
MODF generates a receiver/error CPU interrupt request if the error
interrupt enable bit (ERRIE) is also set. The SPRF, MODF, and OVRF
interrupts share the same CPU interrupt vector. MODF and OVRF can
generate a receiver/error CPU interrupt request. See Figure 10. It is not
possible to enable only MODF or OVRF to generate a receiver/error
CPU interrupt request. However, leaving MODFEN low prevents MODF
from being set.
In a master SPI with the mode fault enable bit (MODFEN) set, the mode
fault flag (MODF) is set if SS becomes ‘0’. A mode fault in a master SPI
causes the following events to occur:
MC68HC08AZ0
232
Serial Peripheral Interface Module (SPI)
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