MC68HC08AZ0 Datasheet, PDF (388/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
msCAN08 Controller (msCAN08)
Table 7. Time segment syntax
SYNC_SEG
Transmit point
Sample point
System expects transitions to occur on
the bus during this period.
A node in transmit mode will transfer a
new value to the CAN bus at this point.
A node in receive mode will sample the
bus at this point. If the three samples per
bit option is selected then this point
marks the position of the third sample.
.
Table 8. Time segment values
TSEG TSEG TSEG TSEG
13
12
11
10
Time segment 1
0
0
0
0
1 Tq clock cycle
0
0
0
1
2 Tq clock cycles
0
0
1
0
3 Tq clock cycles
0
0
1
1
4 Tq clock cycles
.
.
.
.
.
.
.
.
.
.
1
1
1
1
16 Tq clock cycles
TSEG TSEG TSEG
22 21 20
0
0
0
0
0
1
.
.
.
.
.
.
1
1
1
Time segment 2
1 Tq clock cycle
2 Tq clock cycles
.
.
8 Tq clock cycles
msCAN08 receiver
flag register
(CRFLG)
All bits of this register are read and clear only. A flag can be cleared by
writing a 1 to the corresponding bit position. A flag can only be cleared
when the condition which caused the setting is no more valid. Writing a
0 has no effect on the flag setting. Every flag has an associated interrupt
enable flag in the CRIER register. A hard or soft reset will clear the
register.
CRFLG R
$xx04 W
RESET
BIT 7
WUPIF
0
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
RWRNIF TWRNIF RERRIF TERRIF BOFFIF
0
0
0
0
0
Figure 19. Receiver flag register
BIT 1
OVRIF
0
BIT 0
RXF
0
MC68HC08AZ0
386
msCAN08 Controller (msCAN08)
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