MC68HC08AZ0 Datasheet, PDF (435/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Index
PRST bit (PIT reset bit) . . . . . . . . . . . . . . .304
PS[2:0] bits (TIM prescaler select bits) . . 253,
268, 292
PSHH instruction . . . . . . . . . . . . . . . . . . . . .72
PSTOP bit (PIT stop bit) . . . . . . . . . . . . . .304
PTY bit (SCI parity bit). . . . . . . . . . . . . . . .201
PULH instruction . . . . . . . . . . . . . . . . . . . . .72
pulse-width modulation (PWM) . . . . . . . . .282
duty cycle . . .259, 262, 274, 283, 286, 297
initialization . . . . . . . . . . . . . . . . .261, 285
R
R8 bit (SCI received bit 8) . . . . . . . . . . . . .206
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . .35–36
size. . . . . . . . . . . . . . . . . . . . . . . . . .10, 23
stack RAM . . . . . . . . . . . . . . . . . . . . . . .71
RE bit (SCI receiver enable bit). . . . . . . . .204
reset
COP . . . . . . . . . . . . . . . . . . . .93, 159, 164
external . . . . . . . . . . . . . . . . . . . . . . . . .91
external reset pin (RST). . . . . . . . . . . . .14
illegal address . . . . . . . . . . . . . . . .94, 106
illegal opcode . . . . . . . . . . . . . . . . .94, 106
internal . . . . . . . . . . . . . . . . . . . . . . . . .162
low-voltage inhibit (LVI) . . . . . . . . . . . . .94
power-on . . . . . . . . . . . . . . . . . . . .92, 162
RPF bit (SCI reception in progress flag bit) . . .
212
RST pin . . . . . . . . . . . . . . . . . . . . . . . . . . .161
during POR timeout . . . . . . . . . . . . . . . .89
RTI instruction . . . . . . . . . . . . . . . .72, 74, 140
RWU bit (SCI receiver wake-up bit) . . . . .205
S
SBFCR
break clear flag enable bit (BCFE). . . .106
SBK bit (SCI send break bit) . . . . . . .186, 205
SBSR
SIM break STOP/WAIT statur bit (SBSW) .
104
SBSW
SBSR . . . . . . . . . . . . . . . . . . . . . . . . . .104
SCP1–SCP0 bits (SCI baud rate prescaler
bits) . . . . . . . . . . . . . . . . . . . . . . . . 213
SCRF bit (SCI receiver full bit) . . . . . . . . . 209
SCRIE bit (SCI receiver interrupt enable bit) .
194, 209
SCTE bit (SCI transmitter empty bit) 185, 187,
200, 203, 208
SCTIE bit (SCI transmitter interrupt enable bit)
185, 187, 203, 208
serial communications interface module (SCI)
baud rate . . . . . . . . . . . . . . . . . . . . . . . 180
baud rate register (SCBR) . . . . . . . . . . 213
character format . . . . . . . . . . . . . . . . . 202
control register 1 (SCC1). . .184–186, 199
control register 2 (SCC2). . 185–186, 202,
208
control register 3 (SCC3). . 184, 187, 194,
205, 208
data register (SCDR) . . . . . .185, 209, 213
error conditions . . . . . . . . . . . . . . . . . . 194
framing error . . . . . . . . . . . . . . . . 193, 211
I/O pins . . . . . . . . . . . . . . . . . . . . . . . . 198
noise error . . . . . . . . . . . . . . . . . . . . . . 210
overrun error . . . . . . . . . . . . . . . . . . . . 207
parity error . . . . . . . . . . . . . . . . . . . . . . 195
status register 1 (SCS1) . . . . . . . 185, 208
status register 2 (SCS2) . . . . . . . . . . . 212
serial peripheral interface module (SPI)
baud rate . . . . . . . . . . . . . . . . . . . . . . . 246
control register (SPCR) . . . . . . . . . . . . 243
data register (SPDR) . . . . . . . . . . . . . . 249
I/O pins . . . . . . . . . . . . . . . . . . . . . . . . 240
in stop mode . . . . . . . . . . . . . . . . . . . . 238
mode fault error . . . . . . . . . . . . . . . . . . 247
overflow error. . . . . . . . . . . . . . . . . . . . 247
slave select pin . . . . . . . . . . . . . . . . . . 246
status and control register (SPSCR) . . 246
SIM counter
power-on reset. . . . . . . . . . . . . . . . . . . . 95
reset states . . . . . . . . . . . . . . . . . . . . . . 95
stop mode recovery . . . . . . . . . . . . . . . . 95
SIMOSCEN signal . . . . . . . . . . . . . . . . . . 111
SPE bit (SPI enable bit) . . . . . . . . . . . . . . 245
SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . 403
MOTOROLA
Index
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MC68HC08AZ0
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