MC68HC08AZ0 Datasheet, PDF (128/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
VRS[7:4] — VCO range select bits
These read/write bits control the hardware center-of-range linear
multiplier L, which controls the hardware center-of-range frequency
f_VRS. (See PLL circuits on page 112, Programming the PLL on page
115, and PLL control register (PCTL) on page 121).
1 = VRS[7:4] cannot be written when the PLLON bit in the PLL
control register (PCTL) is set. (See Special programming
exceptions on page 116). A value of $0 in the VCO range
select bits disables the PLL and clears the BCS bit in the
PCTL. (See Base clock selector circuit on page 116 and
Special programming exceptions on page 116 for more
information). Reset initializes the bits to $6 to give a default
range multiply value of 6.
NOTE:
The VCO range select bits have built-in protection that prevents them
from being written when the PLL is on (PLLON = 1) and prevents
selection of the VCO clock as the source of the base clock (BCS = 1) if
the VCO range select bits are all clear.
The VCO range select bits must be programmed correctly. Incorrect
programming may result in failure of the PLL to achieve lock.
MC68HC08AZ0
126
Clock Generator Module (CGM)
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