MC68HC08AZ0 Datasheet, PDF (385/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
msCAN08 Controller (msCAN08)
Programmer’s model of control registers
msCAN08 module .
control register
(CMCR1)
CMCR1 R
$xx01 W
RESET
BIT 7
0
BIT 6
0
BIT 5
0
BIT 4
0
BIT 3
0
BIT 2
LOOPB
BIT 1
WUPM
0
0
0
0
0
0
0
= Unimplemented
Figure 16. Module control register 1 (CMCR1)
BIT 0
CLKSRC
0
LOOPB — Loop back self test mode
When this bit is set the msCAN08 performs an internal loop back
which can be used for self test operation: the bit stream output of the
transmitter is fed back to the receiver. The RxCAN input pin is ignored
and the TxCAN output goes to the recessive state (1). Note that in this
state the msCAN08 ignores the ACK bit to insure proper reception of
its own message and will treat messages being received while in
transmission as received messages from remote nodes.
1 = Activate loop back self test mode
0 = Normal operation
WUPM — Wake-up mode
This flag defines whether the integrated low-pass filter is applied to
protect the msCAN08 from spurious wake-ups (see Programmable
wake-up function on page 370).
1 = msCAN08 will wake up the CPU only in case of dominant pulse
on the bus which has a length of at least approximately T_wup.
0 = msCAN08 will wake up the CPU after any recessive to
dominant edge on the CAN bus.
CLKSRC — Clock source
This flag defines which clock source the msCAN08 module is driven
from (see Clock system on page 371).
1 = THE msCAN08 clock source is CGMOUT (see Figure 7).
0 = The msCAN08 clock source is CGMXCLK/2 (see Figure 7).
NOTE: The CMCR1 register can only be written if the SFTRES bit in the
msCAN08 Module Control Register is set
33-can
MOTOROLA
msCAN08 Controller (msCAN08)
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MC68HC08AZ0
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