MC68HC08AZ0 Datasheet, PDF (213/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Serial Communications Interface Module (SCI)
I/O registers
NORMAL FLAG CLEARING SEQUENCE
BYTE 1
READ SCS1
SCRF = 1
OR = 0
READ SCDR
(BYTE 1)
BYTE 2
READ SCS1
SCRF = 1
OR = 0
READ SCDR
(BYTE 2)
BYTE 3
BYTE 4
READ SCS1
SCRF = 1
OR = 0
READ SCDR
(BYTE 3)
DELAYED FLAG CLEARING SEQUENCE
BYTE 1
BYTE 2
READ SCS1
SCRF = 1
OR = 0
READ SCDR
(BYTE 1)
BYTE 3
BYTE 4
READ SCS1
SCRF = 1
OR = 1
READ SCDR
(BYTE 3)
Figure 9. Flag clearing sequence
FE — Receiver framing error bit
This clearable, read-only bit is set when a logic is accepted as the
STOP bit. FE generates an SCI error CPU interrupt request if the
FEIE bit in SCC3 also is set. Clear the FE bit by reading SCS1 with
FE set and then reading the SCDR. Reset clears the FE bit.
1 = Framing error detected
0 = No framing error detected
PE — Receiver parity error bit
This clearable, read-only bit is set when the SCI detects a parity error
in incoming data. PE generates a PE CPU interrupt request if the
PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with
PE set and then reading the SCDR. Reset clears the PE bit.
1 = Parity error detected
0 = No parity error detected
33-sci
MOTOROLA
Serial Communications Interface Module (SCI)
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MC68HC08AZ0
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