MC68HC08AZ0 Datasheet, PDF (436/444 Pages) Motorola, Inc – Advance Information

Index
Freescale Semiconductor, Inc.
SPMSTR bit (SPI master mode bit). .240, 244
SPR1[1:0] bits (SPI baud rate select bits) .248
SPRF bit (SPI receiver full bit). . . . . . . . . .246
SPRIE bit (SPI receiver interrupt enable bit) . .
243
SPTE bit (SPI transmitter empty bit) . . . . .247
SPTIE bit (SPI transmitter interrupt enable bit)
245
SPWOM bit (SPI wired-OR mode bit)240, 244
SRSR
computer operating properly reset bit
(COP) . . . . . . . . . . . . . . . . . . . .106
external reset bit (PIN) . . . . . . . . . . . . .106
illegal address reset bit (ILAD). . . . . . .106
illegal opcode reset bit (ILOP) . . . . . . .106
low-voltage inhibit reset bit (LVI) . . . . .106
power-on reset bit (POR) . . . . . . . . . . .105
SSREC
MORA . . . . . . . . . . . . . . . . . . . . . . . . .137
stack pointer . . . . . . . . . . . . . . . . . . . . . . . .35
stack pointer (SP) . . . . . . . . . . . . . . . . . . . .70
stack RAM . . . . . . . . . . . . . . . . . . . . . . .35, 71
start bit. . . . . . . . . . . . . . . . . . . . . . . .152, 185
SCI data . . . . . . . . . . . . . . . . . . . . . . . .201
stop bit. . . . . . . . . . . . . . . . . . . . . . . . . . . .185
SCI data . . . . . . . . . . . . . . . . . . . .195, 200
STOP bit (STOP enable bit) . . . . . . . . . . .164
STOP instruction . . . 103, 128, 145, 162, 164,
169, 197, 238, 301
STOP mode. . . . . . . . . . . . . . . . . . . . . . . .311
entry timing . . . . . . . . . . . . . . . . . . . . .103
recovery from interrupt break. . . . . . . .103
stop mode . . . . . . . . .145, 161, 169, 212, 301
recovery time . . . . . . . . . . . . . . . . . . . . .89
SWI instruction . . . . . . . . . . .74, 98, 142, 150
system inegration module (SIM)
STOP mode . . . . . . . . . . . . . . . . . . . . .102
system integration module (SIM). . . . .86–106
break flag control register (SBFCR). . .106
break status register (SBSR) . . . . . . . .104
exception control . . . . . . . . . . . . . . . . . .96
reset status register (SRSR) . . . .105, 161
SIM counter . . . . . . . . . . . . . .95, 161–162
WAIT mode . . . . . . . . . . . . . . . . . . . . . 101
T
T8 bit (SCI transmitted bit 8) . . . . . . . . . . . 206
T8 bit (transmitted SCI bit 8) . . . . . . . . . . . 184
TCIE bit (SCI transmission complete interrupt
enable bit) . . . . . . . . . . . . . . . 203, 209
TE bit (SCI transmitter enable bit). . . . . . . 204
TE bit (transmitter enable bit) . . . . . . . . . . 185
thermal characteristics . . . . . . . . . . . . . . . 399
TIMA counter . . . . . . . . . . . . . . . . . . . . . . 264
timer interface module (TIM). . . . . . .277–298
channel registers (TCH0H/L–TCH3H/L) . .
298
timer interface module (TIMA)
channel registers (TACH0H/L–TACH3H/L)
274
channel status and control registers
(TASC0–TASC3) . . . . . . . . . . . 270
clock input pin (PTD3/TACLK). . . . . . . 265
counter modulo registers
(TAMODH:TAMODL) . . . . . . . . 269
counter registers (TACNTH/L). . .268–269
prescaler . . . . . . . . . . . . . . . . . . . . . . . 253
status and control register (TASC) . . . 266
timer interface module (TIMB)
channel registers (TBCH0H/L–TBCH3H/L)
298
channel status and control registers
(TBSC0–TBSC1) . . . . . . . . . . . 294
clock input pin (PTD3/TBCLK). . . . . . . 289
clock input pin (PTD4/TBCLK). . . . . . . 279
counter modulo registers (TBMODH/L) . . .
293
counter modulo registers (TBMODH:TB-
MODL) . . . . . . . . . . . . . . . . . . . 293
counter registers (TBCNTH/L). . .292–293
counter registers (TBCNTH:TBCNTL). 292
status and control register (TBSC) . . . . . . .
290–291
timer module characteristics . . . . . . . . . . . 408
TOF bit (TIM overflow flag bit) . . . . . 267, 291
TOIE bit (TIM overflow interrupt enable bit) . .
MC68HC08AZ0
434
Index
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