MC68HC08AZ0 Datasheet, PDF (46/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
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MC68HC08AZ0
44
External Databus Value D2 - D0
Number of WAIT States
000
0
001
1
010
2
011
3
100
4
101
5
110
6
111
7
Table 2 Data bus values corresponding to number of WAIT states
The pin WSCLK provides the T4 signal to synchronize driving the WAIT
state value onto the External Data lines. Table 3 shows the options
available for the WSCLK pin. The WSCLK can also be disabled.
When external WAIT-state decoding is enabled, the low RF emission
data bus freeze function is disabled for data bus lines D2:0. The address
bus freeze function remains unaffected.
WSCLK1
0
0
1
1
WSCLK0
WSCLK Pin Function
0
Disabled, tri-state
1
T4 + CS0, push/pull
0
T4, push/pull
1
T4, push/pull
Table 3 WSCLK pin function
CS0 used in the WSCLK pin functions is active low, irrespective of the
state of the CS0 pin polarity bit. CS0 and WSCLK are not asserted
during internal access bus cycles. The term <T4 + CS0> is therefore an
active low signal.
Examples of external WAIT state selection are shown in Figure 8,
Figure 9 and Figure 10
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