MC68HC08AZ0 Datasheet, PDF (433/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Index
bus timing register 1 (CBTR1) . . . . . . .385
clock system . . . . . . . . . . . . . . . . . . . .371
control register structure . . . . . . . . . . .380
CPU WAIT mode . . . . . . . . . . . . . . . . .370
Data length register (DLR) . . . . . . . . . .378
Data segment registers (DSRn). . . . . .378
external pins. . . . . . . . . . . . . . . . . . . . .354
Identifier Acceptance Control Register (CI-
DAC) . . . . . . . . . . . . . . . . . . . . .392
identifier acceptance filter . . . . . . . . . .360
Identifier Acceptance Registers
(CIDAR0-3) . . . . . . . . . . . . . . . .394
Identifier Mask Registers (CIDMR0-3) .395
identifier registers (IDRn) . . . . . . . . . . .376
internal sleep mode . . . . . . . . . . . . . . .368
interrupt acknowledge . . . . . . . . . . . . .364
interrupt vectors . . . . . . . . . . . . . . . . . .364
interrupts . . . . . . . . . . . . . . . . . . . . . . .361
memory map . . . . . . . . . . . . . . . . . . . .374
message buffer organization . . . . . . . .358
message buffer outline. . . . . . . . . . . . .375
message storage . . . . . . . . . . . . . . . . .355
module control register (CMCR0) . . . .381
module control register (CMCR1) . . . .383
programmable wake-up function . . . . .370
Receive Error Counter (CRXERR). . . .393
receive structures. . . . . . . . . . . . . . . . .356
receiver flag register (CRFLG). . . . . . .386
receiver interrupt enable register (CRIER).
389
Transmit buffer priority registers (TBPR) . .
379
Transmit Error Counter (CTXERR) . . .394
transmit structures . . . . . . . . . . . . . . . .359
Transmitter Control Register (CTCR) .391
Transmitter Flag Register (CTFLG) . . .390
MSxA/B bits (TIM mode select bits) 272, 274,
295, 298
N
N bit
CCR . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
NEIE bit (SCI noise error interrupt enable bit) .
194, 210
NEIE bit (SCI receiver noise error interrupt en-
able bit) . . . . . . . . . . . . . . . . . . . . . 207
NF bit (SCI noise flag bit) . . . . . . . . . 194, 210
O
OR bit (SCI receiver overrun bit). . . . 194, 210
ordering information
literature distribution centers . . . . . . . . 437
Mfax. . . . . . . . . . . . . . . . . . . . . . . . . . . 438
Web server . . . . . . . . . . . . . . . . . . . . . 438
Web site. . . . . . . . . . . . . . . . . . . . . . . . 438
ORIE bit (SCI overrun interrupt enable bit) . . .
194
ORIE bit (SCI receiver overrun interrupt en-
able bit) . . . . . . . . . . . . . . . . . . . . . 207
OSC1 pin . . . . . . . . . . . . . . . . . . . . . . 14, 118
OSC2 pin . . . . . . . . . . . . . . . . . . . . . . . . . . 14
oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . 162
oscillator enable signal (SIMOSCEN) . . . . 119
oscillator pins
OSC1. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
output compare . . . . . . . . . . . . .256, 281, 298
buffered . . . . . . . . . . . . . . . . . . . . 257, 282
unbuffered . . . . . . . . . . . . . . . . . . 256, 281
OVRF bit (SPI overflow bit). . . . . . . . . . . . 247
P
page zero . . . . . . . . . . . . . . . . . . . . . . . . . . 71
parity
SCI module . . . . . . . . . . . . . . . . . 195, 199
PBWC
acquisition mode bit (ACQ) . . . . . . . . . 124
automatic bandwidth control bit (AUTO) . .
123
crystal loss detect bit (XLD). . . . . . . . . 124
lock indicator bit (LOCK) . . . . . . . . . . . 123
PCTL
base clock select bit (BCS) . . . . . . . . . 122
PLL interrupt enable bit (PLLIE) . . . . . 121
PLL interrupt flag bit (PLLF)
PLLF
PCTL121
MOTOROLA
Index
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MC68HC08AZ0
431