MC68HC08AZ0 Datasheet, PDF (396/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
msCAN08 Controller (msCAN08)
msCAN08 Transmit
Error Counter
(CTXERR)
BIT 7
CTXERR R TXERR7
$xx0F W
RESET 0
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
TXERR6 TXERR5 TXERR4 TXERR3 TXERR2
0
0
0
0
0
= Unimplemented
Figure 24. Transmit Error Counter
BIT 1
TXERR1
0
BIT 0
TXERR0
0
This register reflects the status of the msCAN08 transmit error counter.
The register is read only.
NOTE: Both error counters may only be read when in Sleep or SOft Reset
Mode.
msCAN08
Identifier
Acceptance
Registers
(CIDAR0-3)
On reception each message is written into the background receive
buffer. The CPU is only signalled to read the message however, if it
passes the criteria in the identifier acceptance and identifier mask
registers (accepted); otherwise, the message will be overwritten by the
next message (dropped).
The acceptance registers of the msCAN08 are applied on the IDR0 to
IDR3 registers of incoming messages in a bit by bit manner.
For extended identifiers all four acceptance and mask registers are
applied. For standard identifiers only the first two (IDAR0, IDAR1) are
applied. In the latter case it is required to program the mask register
CIDMR1 in the three last bits (AC2 - AC0) to ‘don’t care’.
MC68HC08AZ0
394
msCAN08 Controller (msCAN08)
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44-can
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