MC68HC08AZ0 Datasheet, PDF (117/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
Functional description
• Software must wait a given time, t_AL, after entering tracking mode
before selecting the PLL as the clock source to CGMOUT (BCS =
1).
• The LOCK bit is disabled.
• CPU interrupts from the CGM are disabled.
Programming the
PLL
The following procedure shows how to program the PLL.
NOTE: The round function in the following equations means that the real
number should be rounded to the nearest integer number.
1. Choose the desired bus frequency, f_BUSDES.
2. Calculate the desired VCO frequency (four times the
desired bus frequency).
f_VCLKDES = 4 × f_BUDES
3. Choose a practical PLL reference frequency, f_RCLK.
4. Select a VCO frequency multiplier, N.
N = round -f--^V----^C----^L---^K----^D----^E---^S-
f_RCLK
5. Calculate and verify the adequacy of the VCO and bus
frequencies f_VCLK and f_BUS.
f_VCLK = N × f_RCLK
f_BUS = (f_VCLK) ⁄ 4
6. Select a VCO linear range multiplier, L.
L = round -f--^V----^C----^L---^K--
f_NOM
where f_NOM = 4.9152MHz
7. Calculate and verify the adequacy of the VCO programmed
center-of-range frequency f_VRS.
f_VRS = (L)f_NOM
9-cgm
MOTOROLA
Clock Generator Module (CGM)
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MC68HC08AZ0
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