MC68HC08AZ0 Datasheet, PDF (206/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Serial Communications Interface Module (SCI)
ILIE — Idle line interrupt enable bit
This read/write bit enables the IDLE bit to generate SCI receiver CPU
interrupt requests. Reset clears the ILIE bit.
1 = IDLE enabled to generate CPU interrupt requests
0 = IDLE not enabled to generate CPU interrupt requests
NOTE:
When SCI receiver DMA service requests are enabled (DMARE = 1),
then SCI receiver CPU interrupt requests are disabled, and the state of
the ILIE bit has no effect.
TE — Transmitter enable bit
Setting this read/write bit begins the transmission by sending a
preamble of 10 or 11 ‘1’s from the transmit shift register to the
PTE2/TxD pin. If software clears the TE bit, the transmitter completes
any transmission in progress before the PTE0/TxD returns to the idle
condition (’1’). Clearing and then setting TE during a transmission
queues an idle character to be sent after the character currently being
transmitted. Reset clears the TE bit.
1 = Transmitter enabled
0 = Transmitter disabled
NOTE: Writing to the TE bit is not allowed when the enable SCI bit (ENSCI) is
clear. ENSCI is in SCI control register 1.
RE — Receiver enable bit
Setting this read/write bit enables the receiver. Clearing the RE bit
disables the receiver but does not affect receiver interrupt flag bits.
Reset clears the RE bit.
1 = Receiver enabled
0 = Receiver disabled
NOTE: Writing to the RE bit is not allowed when the enable SCI bit (ENSCI) is
clear. ENSCI is in SCI control register 1.
MC68HC08AZ0
204
Serial Communications Interface Module (SCI)
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