MC68HC08AZ0 Datasheet, PDF (293/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Timer Interface Module B (TIMB)
I/O Registers
Bit 7
6
5
4
3
2
1
Bit 0
TBSC
$0040
Read:
Write:
TOF
0
TOIE
0
TSTOP
TRST
0
PS2
PS1
PS0
Reset: 0
0
1
0
0
0
0
0
= Unimplemented
Figure 11. TIMB status and control register (TBSC)
TOF — TIMB overflow flag bit
This read/write flag is set when the TIMB counter resets to $0000 after
reaching the modulo value programmed in the TIMB counter modulo
registers. Clear TOF by reading the TIMB status and control register
when TOF is set and then writing a logic zero to TOF. If another TIMB
overflow occurs before the clearing sequence is complete, then
writing logic zero to TOF has no effect. Therefore, a TOF interrupt
request cannot be lost due to inadvertent clearing of TOF. Reset
clears the TOF bit. Writing a logic one to TOF has no effect.
1 = TIMB counter has reached modulo value
0 = TIMB counter has not reached modulo value
TOIE — TIMB overflow interrupt enable bit
This read/write bit enables TIMB overflow interrupts when the TOF bit
becomes set. Reset clears the TOIE bit.
1 = TIMB overflow interrupts enabled
0 = TIMB overflow interrupts disabled
TSTOP — TIMB stop bit
This read/write bit stops the TIMB counter. Counting resumes when
TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIMB
counter until software clears the TSTOP bit.
1 = TIMB counter stopped
0 = TIMB counter active
NOTE: Do not set the TSTOP bit before entering wait mode if the TIMB is
required to exit wait mode.
15-timb
MOTOROLA
Timer Interface Module B (TIMB)
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MC68HC08AZ0
291