MC68HC08AZ0 Datasheet, PDF (337/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
I/O Ports
Port C
Data direction
register C (DDRC)
Data direction register C determines whether each port C pin is an input
or an output. Writing a logic one to a DDRC bit enables the output buffer
for the corresponding port C pin; a logic zero disables the output buffer.
Bit 7
6
5
4
3
2
1
Bit 0
DDRC
$0006
Read: _MCLKE
Write:
N
0
DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 8. Data direction register C (DDRC)
MCLKEN — MCLK enable bit
This read/write bit enables MCLK to be an output signal on PTC2. If
MCLK is enabled, PTC2 is under the control of MCLKEN. Reset
clears this bit.
1 = MCLK output enabled
0 = MCLK output disabled
DDRC[5:0] — Data direction register C bits
These read/write bits control port C data direction. Reset clears
DDRC[7:0], configuring all port C pins as inputs.
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
NOTE: Avoid glitches on port C pins by writing to the port C data register before
changing data direction register C bits from 0 to 1.
Figure 9 shows the port C I/O logic.
9-io
MOTOROLA
I/O Ports
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MC68HC08AZ0
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