MC68HC08AZ0 Datasheet, PDF (340/444 Pages) Motorola, Inc – Advance Information

I/O Ports
Freescale Semiconductor, Inc.
(TBSC) on page 290). When not selected as the TIM clock,
PTD6/TAClk and PTD4/TBCLK are available for general purpose I/O.
While TACLK/TBCLK are selected, corresponding DDRD bits have
no effect.
Data direction
register D (DDRD)
Data direction register D determines whether each port D pin is an input
or an output. Writing a logic one to a DDRD bit enables the output buffer
for the corresponding port D pin; a logic zero disables the output buffer.
Bit 7
6
5
4
3
2
1
Bit 0
DDRD
$0007
Read:
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 11. Data direction register D (DDRD)
DDRD[7:0] — Data direction register D bits
These read/write bits control port D data direction. Reset clears
DDRD[7:0], configuring all port D pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE: Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Figure 12 shows the port D I/O logic.
When bit DDRDx is a logic one, reading address $0003 reads the PTDx
data latch. When bit DDRDx is a logic zero, reading address $0003
reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 5 summarizes the
operation of the port D pins.
MC68HC08AZ0
338
I/O Ports
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