MC68HC08AZ0 Datasheet, PDF (386/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
msCAN08 Controller (msCAN08)
msCAN08 bus
timing register 0
(CBTR0)
CBTR0 R
$xx02 W
RESET
BIT 7
SJW1
0
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
SJW0 BRP5 BRP4 BRP3 BRP2
0
0
0
0
0
Figure 17. Bus timing register 0
BIT 1
BRP1
0
BIT 0
BRP0
0
SJW1, SJW0 — Synchronization jump width
The synchronization jump width defines the maximum number of time
quanta (Tq) clock cycles by which a bit may be shortened, or
lengthened, to achieve resynchronization on data transitions on the
bus (see Table 5).
SJW1
0
0
1
1
Table 5. Synchronization jump width
SJW0
0
1
0
1
Synchronization jump width
1 Tq clock cycle
2 Tq clock cycles
3 Tq clock cycles
4 Tq clock cycles
BRP5–BRP0 — Baud Rate Prescaler
These bits determine the time quanta (Tq) clock, which is used
to build up the individual bit timing, according to Table 6.
MC68HC08AZ0
384
BRP5
0
0
0
0
:
:
1
Table 6. Baud rate prescaler
BRP4
0
0
0
0
:
:
1
BRP3
0
0
0
0
:
:
1
BRP2
0
0
0
0
:
:
1
BRP1
0
0
1
1
:
:
1
BRP0
0
1
0
1
:
:
1
Prescaler
value (P)
1
2
3
4
:
:
64
msCAN08 Controller (msCAN08)
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