MC68HC08AZ0 Datasheet, PDF (200/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Serial Communications Interface Module (SCI)
SCI during break module interrupts
The system integration module (SIM) controls whether status bits in
other modules can be cleared during interrupts generated by the break
module. The BCFE bit in the SIM break flag control register (SBFCR)
enables software to clear status bits during the break state. See SIM
break flag control register (SBFCR) on page 106.
To allow software to clear status bits during a break interrupt, write a ‘1’
to the BCFE bit. If a status bit is cleared during the break state, it remains
cleared when the MCU exits the break state.
To protect status bits during the break state, write a ‘0’ to the BCFE bit.
With BCFE at 0 0 0 (its default state), software can read and write I/O
registers during the break state without affecting status bits. Some status
bits have a two-step read/write clearing procedure. If software does the
first step on such a bit before the break, the bit cannot change during the
break state as long as BCFE is at ‘0’. After the break, doing the second
step clears the status bit.
I/O signals
Port E shares two of its pins with the SCI module. The two SCI I/O pins are:
• PTE0/TxD — Transmit data
• PTE1/RxD — Receive data
PTE0/TxD (transmit
data)
The PTE0/TxD pin is the serial data output from the SCI transmitter. The
SCI shares the PTE0/TxD pin with port E. When the SCI is enabled, the
PTE0/TxD pin is an output regardless of the state of the DDRE0 bit in
data direction register E (DDRE).
PTE1/RxD (receive
data)
The PTE1/RxD pin is the serial data input to the SCI receiver. The SCI
shares the PTE1/RxD pin with port E. When the SCI is enabled, the
PTE1/RxD pin is an input regardless of the state of the DDRE1 bit in data
direction register E (DDRE).
MC68HC08AZ0
198
Serial Communications Interface Module (SCI)
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