MC68HC08AZ0 Datasheet, PDF (214/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Serial Communications Interface Module (SCI)
SCI status register
2 (SCS2)
SCI status register 2 contains flags to signal the following conditions:
• Break character detected
• Incoming data
SCS2
$0017
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
0
0
0
0
0
0
= Unimplemented
Figure 10. SCI status register 2 (SCS2)
1
BKF
Bit 0
RPF
0
0
BKF — Break flag bit
This clearable, read-only bit is set when the SCI detects a break
character on the PTE1/RxD pin. In SCS1, the FE and SCRF bits are
also set. In 9-bit character transmissions, the R8 bit in SCC3 is
cleared. BKF does not generate a CPU interrupt request. Clear BKF
by reading SCS2 with BKF set and then reading the SCDR. Once
cleared, BKF can become set again only after ‘1’s again appear on
the PTE1/RxD pin followed by another break character. Reset clears
the BKF bit.
1 = Break character detected
0 = No break character detected
RPF — Reception in progress flag bit
This read-only bit is set when the receiver detects a ‘0’ during the RT1
time period of the start bit search. RPF does not generate an interrupt
request. RPF is reset after the receiver detects false start bits (usually
from noise or a baud rate mismatch, or when the receiver detects an
idle character. Polling RPF before disabling the SCI module or
entering STOP mode can show whether a reception is in progress.
1 = Reception in progress
0 = No reception in progress
MC68HC08AZ0
212
Serial Communications Interface Module (SCI)
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