MC68HC08AZ0 Datasheet, PDF (295/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Timer Interface Module B (TIMB)
I/O Registers
NOTE:
If you read TBCNTH during a break interrupt, be sure to unlatch
TBCNTL by reading TBCNTL before exiting the break interrupt.
Otherwise, TBCNTL retains the value latched during the break.
Bit 7
6
5
4
3
2
1
TBCNTH ^{Read: Bit 15}
14
13
12
11
10
9
$0041 _Write:
Reset: 0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
TBCNTL ^{Read: Bit 7}
6
5
4
3
2
1
$0042 _Write:
0
0
0
0
0
0
0
Reset:
= Unimplemented
Figure 12. TIMB counter registers (TBCNTH:TBCNTL)
Bit 0
Bit 8
0
Bit 0
Bit 0
0
TIMB counter
modulo registers
(TBMODH:TBMOD)
The read/write TIMB modulo registers contain the modulo value for the
TIMB counter. When the TIMB counter reaches the modulo value, the
overflow flag (TOF) becomes set, and the TIMB counter resumes
counting from $0000 at the next clock. Writing to the high byte
(TBMODH) inhibits the TOF bit and overflow interrupts until the low byte
(TBMODL) is written. Reset sets the TIMB counter modulo registers.
Bit 7
6
5
4
3
2
1
Bit 0
TBMODH ^Read:
$0043 _Write:
Bit 15
14
13
12
11
10
9
Bit 8
Reset: 1
1
1
1
1
1
1
1
Bit 7
6
5
4
3
2
1
Bit 0
TBMODL ^Read:
$0044 _Write:
Bit 7
6
5
4
3
2
1
Bit 0
Reset: 1
1
1
1
1
1
1
1
Figure 13. TIMB counter modulo registers (TBMODH:TBMODL)
17-timb
MOTOROLA
Timer Interface Module B (TIMB)
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MC68HC08AZ0
293