MC68HC08AZ0 Datasheet, PDF (52/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
EBI
EBI control registers
The following I/O registers control and monitor operation of the EBI:-
• EBI Control Register (EBIC)
• Chip-Select Control Register (EBICS)
EBI control register
EBIC ^Read:
$003B _Write:
Reset
:
Bit 7
0
6
5
4
3
2
IRV
MODE C0WS WSCLK1 WSCLK0
0
0
0
0
0
0
= Unimplemented
Figure 11 EBI control register (EBIC)
1
CSC1
0
0
CSC0
0
IRVIRV — Internal read visibility bit
This function is included for easy-debug of the customer application.
1 = The REB and WEB are active during IRV, to allow creation of
an ECLK. Enabled chip selects are active as well, and all
internal bus activity is externally visible.
0 = In normal user operation IRV should be off to prevent possible
bus contention.
MODE — EBI operating mode
1 = Low Noise
0 = High Performance
C0WS — Chip select 0 WAIT state control
1 = Externally Controlled
0 = Internally Controlled.
MC68HC08AZ0
50
EBI
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14-ebi
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