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MC68HC08AZ0 Datasheet, PDF (43/444 Pages) Motorola, Inc – Advance Information
Freescale Semiconductor, Inc.
EBI
Module I/O signal descriptions
Internal WAIT state
Ð IWS
The internal WAIT state signal is an output from the EBI module. It is
connected to the IMREQB (in the IBUS), which suspends the CPU state
(but not the internal clocks). The IMREQB signal delay is software
controlled for CSI and either software or hardware controlled for
CS0.This signal will be disabled for internal accesses.
External address
bus Ð A[15:0]
The external address bus are the output address signals from the EBI
module. They provide addressing information to the external devices. In
Low Noise mode the values on these lines remain at the last driven state
between external accesses.
Chip-selects Ð
CS1, CS0
The chip-selects are output control signals from the EBI module. They
enable external devices at their programmed addresses.
External data bus Ð
DB[7:0]
The external data bus are three-state bidirectional data signals to the
EBI module. These signals provide the data path between the MCU and
all external devices. In Low Noise mode the values on these lines
remain at the last driven state between external accesses.
External read Ð REB
The external read is an output control signal from the EBI module. When
REB is asserted, a read cycle starts and data is transferred from an
external device to the internal data bus. This signal is asserted only for
external accesses, or when the IRV bit is set.
External write Ð
WEB
The external write is an output control signal to the EBI module. When
WEB is asserted, a write cycle starts and data is transferred to an
external device from the internal data bus. This signal is asserted only
for external accesses or when the IRV bit is set.
WAIT state clock Ð
WSCLK
The WAIT state clock is used to insert the correct number of WAIT states
into each bus cycle when the ‘external WAIT states’ operating mode is
selected for CS0.
5-ebi
MOTOROLA
EBI
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MC68HC08AZ0
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