MC68HC08AZ0 Datasheet, PDF (48/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
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CSC[1:0]. The peripheral will be multiply mapped within this address
space. Whenever CS0 is asserted and the CS0 WAIT state control is
configured for external control (C0WS =1), internal logic will direct the
WAIT state generator to use the data bus as the source of the number
of WAIT states to be inserted. In this case, the value $111 will be driven
onto D2:0 during T4 which will instruct the WAIT state generator to insert
7 WAIT states (equivalent to a 1uS bus cycle for an 8MHz bus clock).
The number of WAIT states for CS1 is selected internally based on the
contents of CS1WS1:0 bits and may between 0 and 3 bus cycles.
In Figure 9, the application requires different WAIT states for program
memory, RAM and peripheral bus cycles. One of the chip selects must
therefore be subdivided into two address spaces, each with a different
number of WAIT states associated with it. A simple decode of the upper
2 address lines provides an address range of $0000-$1FFF for the
peripheral and drives External Data bus line D1 high during T4 when
within that address range, thus requesting 2 WAIT states. In this
implementation, the peripheral map is duplicated with the address range
$0000 to $0FFF as well as the required $1000 to $1FFF. In order to
prevent internal accesses effecting the peripheral, CS0 is used as a
further enable to both devices within this address space. CS0 is not
asserted for internal accesses within its address space.
WSCLK is programmed to generate CS0+T4 which will go low during T4
whenever the address is within the CS0 range as defined by CSC[1:0].
The number of WAIT states for CS1 is selected internally based on the
contents of CS1WS1:0 bits and may between 0 and 3 bus cycles.
MC68HC08AZ0
46
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