M1AFS600-PQ208 Datasheet, PDF (98/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Device Architecture
Table 2-36 • Analog Block Pin Description (continued)
Signal Name
Number
of Bits Direction
GDON0 to GDON9
10
Input
TMSTB0 to TMSTB9
10
Input
DAVOUT0, DACOUT0, DATOUT0 30
to
DAVOUT9, DACOUT9, DATOUT9
DENAV0, DENAC0, DENAT0 to
30
DENAV9, DENAC9, DENAT9
AV0
1
AC0
1
AG0
1
AT0
1
ATRETURN01
1
Output
Input
Input
Input
Output
Input
Input
AV1
AC1
AG1
AT1
AV2
AC2
AG2
AT2
ATRETURN23
1
Input
1
Input
1
Output
1
Input
1
Input
1
Input
1
Output
1
Input
1
Input
AV3
AC3
AG3
AT3
AV4
AC4
AG4
AT4
ATRETURN45
1
Input
1
Input
1
Output
1
Input
1
Input
1
Input
1
Output
1
Input
1
Input
AV5
AC5
AG5
AT5
AV6
AC6
1
Input
1
Input
1
Output
1
Input
1
Input
1
Input
Function
Location of
Details
Control to power MOS – 1 per quad Analog Quad
Temperature monitor strobe – 1 per Analog Quad
quad; active high
Digital outputs – 3 per quad
Analog Quad
Digital input enables – 3 per quad
Analog Quad
Analog Quad 0
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Temperature monitor return shared by Analog Quad
Analog Quads 0 and 1
Analog Quad 1
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad 2
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Temperature monitor return shared by Analog Quad
Analog Quads 2 and 3
Analog Quad 3
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad 4
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Temperature monitor return shared by Analog Quad
Analog Quads 4 and 5
Analog Quad 5
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad 6
Analog Quad
Analog Quad
2-82
Revision 4