M1AFS600-PQ208 Datasheet, PDF (34/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Device Architecture
Table 2-7 • AFS250 Global Resource Timing
Commercial Temperature Range Conditions: T_J = 70°C, Worst-Case VCC = 1.425 V
–2
–1
Std.
Parameter
Description
Min.¹ Max.² Min.¹ Max.² Min.¹ Max.² Units
t_RCKL
Input Low Delay for Global Clock
0.89 1.12 1.02 1.27 1.20 1.50 ns
t_RCKH
Input High Delay for Global Clock
0.88 1.14 1.00 1.30 1.17 1.53 ns
t_RCKMPWH Minimum Pulse Width High for Global Clock
ns
t_RCKMPWL Minimum Pulse Width Low for Global Clock
ns
t_RCKSW
Maximum Skew for Global Clock
0.26
0.30
0.35 ns
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.
Table 2-8 • AFS090 Global Resource Timing
Commercial Temperature Range Conditions: T_J = 70°C, Worst-Case VCC = 1.425 V
–2
–1
Std.
Parameter
Description
Min.¹ Max.² Min.¹ Max.² Min.¹ Max.²
Units
t_RCKL
Input Low Delay for Global Clock
0.84 1.07 0.96 1.21 1.13 1.43 ns
t_RCKH
Input High Delay for Global Clock
0.83 1.10 0.95 1.25 1.12 1.47 ns
t_RCKMPWH Minimum Pulse Width High for Global Clock
ns
t_RCKMPWL Minimum Pulse Width Low for Global Clock
ns
t_RCKSW
Maximum Skew for Global Clock
0.27
0.30
0.36 ns
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.
2-18
Revision 4