M1AFS600-PQ208 Datasheet, PDF (104/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Device Architecture
Direct Digital Input
The AV, AC, and AT pads can also be configured as high-voltage digital inputs (Figure 2-69). As these
pads are 12 V–tolerant, the digital input can also be up to 12 V. However, the frequency at which these
pads can operate is limited to 10 MHz.
To enable one of these analog input pads to operate as a digital input, its corresponding Digital Input
Enable (DENAxy) pin on the Analog Block must be pulled High, where x is either V, C, or T (for AV, AC,
or AT pads, respectively) and y is in the range 0 to 9, corresponding to the appropriate Analog Quad.
When the pad is configured as a digital input, the signal will come out of the Analog Block macro on the
appropriate DAxOUTy pin, where x represents the pad type (V for AV pad, C for AC pad, or T for AT pad)
and y represents the appropriate Analog Quad number. Example: If the AT pad in Analog Quad 5 is
configured as a digital input, it will come out on the DATOUT5 pin of the Analog Block macro.
Off-Chip
Pads
On-Chip
AV
Voltage
Monitor Block
Prescaler
AC
Current
Monitor Block
AG
Gate
Driver
AT
Temperature
Monitor Block
Analog Quad
Prescaler
Prescaler
Digital
Input
Digital
Input
Current
Monitor / Instr
Amplifier
Power
MOSFET
Gate Driver
To FPGA
(DAVOUTx)
To Analog MUX
To FPGA
(DACOUTx)
From FPGA
(GDONx)
To Analog MUX
Figure 2-69 • Analog Quad Direct Digital Input Configuration
Digital
Input
Temperature
Monitor
To FPGA
(DATOUTx)
To Analog MUX
2-88
Revision 4