M1AFS600-PQ208 Datasheet, PDF (244/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Device Architecture
User-Defined Supply Pins
VREF
I/O Voltage Reference
Reference voltage for I/O minibanks. Both AFS600 and AFS1500 (north bank only) support Microsemi
Pro I/O. These I/O banks support voltage reference standard I/O. The VREF pins are configured by the
user from regular I/Os, and any I/O in a bank, except JTAG I/Os, can be designated as the voltage
reference I/O. Only certain I/O standards require a voltage reference—HSTL (I) and (II), SSTL2 (I) and
(II), SSTL3 (I) and (II), and GTL/GTL+. One VREF pin can support the number of I/Os available in its
minibank.
VAREF
Analog Reference Voltage
The Fusion device can be configured to generate a 2.56 V internal reference voltage that can be used by
the ADC. While using the internal reference, the reference voltage is output on the VAREF pin for use as
a system reference. If a different reference voltage is required, it can be supplied by an external source
and applied to this pin. The valid range of values that can be supplied to the ADC is 1.0 V to 3.3 V. When
VAREF is internally generated by the Fusion device, a bypass capacitor must be connected from this pin
to ground. The value of the bypass capacitor should be between 3.3 µF and 22 µF, which is based on the
needs of the individual designs. The choice of the capacitor value has an impact on the settling time it
takes the VAREF signal to reach the required specification of 2.56 V to initiate valid conversions by the
ADC. If the lower capacitor value is chosen, the settling time required for VAREF to achieve 2.56 V will
be shorter than when selecting the larger capacitor value. The above range of capacitor values supports
the accuracy specification of the ADC, which is detailed in the datasheet. Designers choosing the smaller
capacitor value will not obtain as much margin in the accuracy as that achieved with a larger capacitor
value. Depending on the capacitor value selected in the Analog System Builder, a tool in Libero SoC, an
automatic delay circuit will be generated using logic tiles available within the FPGA to ensure that VAREF
has achieved the 2.56 V value. Microsemi recommends customers use 10 µF as the value of the bypass
capacitor. Designers choosing to use an external VAREF need to ensure that a stable and clean VAREF
source is supplied to the VAREF pin before initiating conversions by the ADC. Designers should also
make sure that the ADCRESET signal is deasserted before initiating valid conversions.²
If the user connects VAREF to external 3.3 V on their board, the internal VAREF driving OpAmp tries to
bring the pin down to the nominal 2.56 V until the device is programmed and up/functional. Under this
scenario, it is recommended to connect an external 3.3 V supply through a ~1 KOhm resistor to limit
current, along with placing a 10-100nF capacitor between VAREF and GNDA.
User Pins
I/O
User Input/Output
The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are
compatible with the I/O standard selected. Unused I/O pins are configured as inputs with pull-up
resistors.
During programming, I/Os become tristated and weakly pulled up to VCCI. With the VCCI and VCC
supplies continuously powered up, when the device transitions from programming to operating mode, the
I/Os get instantly configured to the desired user configuration.
Unused I/Os are configured as follows:
• Output buffer is disabled (with tristate value of high impedance)
• Input buffer is disabled (with tristate value of high impedance)
• Weak pull-up is programmed
Axy
Analog Input/Output
Analog I/O pin, where x is the analog pad type (C = current pad, G = Gate driver pad, T = Temperature
pad, V = Voltage pad) and y is the Analog Quad number (0 to 9). There is a minimum 1 M to ground on
AV, AC, and AT. This pin can be left floating when it is unused.
2. The ADC is functional with an external reference down to 1V, however to meet the performance parameters highlighted in the
datasheet refer to the VAREF specification in Table 3-2 on page 3-3.
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