M1AFS600-PQ208 Datasheet, PDF (18/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Device Architecture
The system application, Level 3, is the larger user application that utilizes one or more applets. Designing
at the highest level of abstraction supported by the Fusion technology stack, the application can be easily
created in FPGA gates by importing and configuring multiple applets.
In fact, in some cases an entire FPGA system design can be created without any HDL coding.
An optional MCU enables a combination of software and HDL-based design methodologies. The MCU
can be on-chip or off-chip as system requirements dictate. System portioning is very flexible, allowing the
MCU to reside above the applets or to absorb applets, or applets and backbone, if desired.
The Fusion technology stack enables a very flexible design environment. Users can engage in design
across a continuum of abstraction from very low to very high.
Core Architecture
VersaTile
Based upon successful ProASIC3/E logic architecture, Fusion devices provide granularity comparable to
gate arrays. The Fusion device core consists of a sea-of-VersaTiles architecture.
As illustrated in Figure 2-2, there are four inputs in a logic VersaTile cell, and each VersaTile can be
configured using the appropriate flash switch connections:
• Any 3-input logic function
• Latch with clear or set
• D-flip-flop with clear or set
• Enable D-flip-flop with clear or set (on a 4th input)
VersaTiles can flexibly map the logic and sequential gates of a design. The inputs of the VersaTile can be
inverted (allowing bubble pushing), and the output of the tile can connect to high-speed, very-long-line
routing resources. VersaTiles and larger functions are connected with any of the four levels of routing
hierarchy.
When the VersaTile is used as an enable D-flip-flop, the SET/CLR signal is supported by a fourth input,
which can only be routed to the core cell over the VersaNet (global) network.
The output of the VersaTile is F2 when the connection is to the ultra-fast local lines, or YL when the
connection is to the efficient long-line or very-long-line resources (Figure 2-2).
0
Data
1
X3
0
CLK
1
X2
Y
0
1
Pin 1
0
F2
1
YL
CLR/
Enable
X1
CLR
XC*
Legend:
Via (hard connection) Switch (flash connection)
Ground
Note: *This input can only be connected to the global clock distribution network.
Figure 2-2 • Fusion Core VersaTile
2-2
Revision 4