M1AFS600-PQ208 Datasheet, PDF (70/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Device Architecture
Flash Memory Block Characteristics
CLK
RESET
Active Low, Asynchronous
BUSY
Figure 2-44 • Reset Timing Diagram
Table 2-25 • Flash Memory Block Timing
Commercial Temperature Range Conditions: T_J = 70°C, Worst-Case VCC = 1.425 V
Parameter
t_CLK2RD
t_CLK2BUSY
t_CLK2STATUS
t_DSUNVM
t_DHNVM
t_ASUNVM
t_AHNVM
t_SUDWNVM
t_HDDWNVM
t_SURENNVM
t_HDRENNVM
t_SUWENNVM
t_HDWENNVM
t_SUPROGNVM
t_HDPROGNVM
t_SUSPAREPAGE
t_HDSPAREPAGE
t_SUAUXBLK
t_HDAUXBLK
t_SURDNEXT
t_HDRDNEXT
t_SUERASEPG
t_HDERASEPG
t_{SUUNPROTECTPG}
t_{HDUNPROTECTPG}
t_SUDISCARDPG
t_HDDISCARDPG
t_SUOVERWRPRO
t_HDOVERWRPRO
Description
Clock-to-Q in 5-cycle read mode of the Read Data
Clock-to-Q in 6-cycle read mode of the Read Data
Clock-to-Q in 5-cycle read mode of BUSY
Clock-to-Q in 6-cycle read mode of BUSY
Clock-to-Status in 5-cycle read mode
Clock-to-Status in 6-cycle read mode
Data Input Setup time for the Control Logic
Data Input Hold time for the Control Logic
Address Input Setup time for the Control Logic
Address Input Hold time for the Control Logic
Data Width Setup time for the Control Logic
Data Width Hold time for the Control Logic
Read Enable Setup time for the Control Logic
Read Enable Hold Time for the Control Logic
Write Enable Setup time for the Control Logic
Write Enable Hold Time for the Control Logic
Program Setup time for the Control Logic
Program Hold time for the Control Logic
SparePage Setup time for the Control Logic
SparePage Hold time for the Control Logic
Auxiliary Block Setup Time for the Control Logic
Auxiliary Block Hold Time for the Control Logic
ReadNext Setup Time for the Control Logic
ReadNext Hold Time for the Control Logic
Erase Page Setup Time for the Control Logic
Erase Page Hold Time for the Control Logic
Unprotect Page Setup Time for the Control Logic
Unprotect Page Hold Time for the Control Logic
Discard Page Setup Time for the Control Logic
Discard Page Hold Time for the Control Logic
Overwrite Protect Setup Time for the Control Logic
Overwrite Protect Hold Time for the Control Logic
–2
7.99
5.03
4.95
4.45
11.24
4.48
1.92
0.00
2.76
0.00
1.85
0.00
3.85
0.00
2.37
0.00
2.16
0.00
3.74
0.00
3.74
0.00
2.17
0.00
3.76
0.00
2.01
0.00
1.88
0.00
1.64
0.00
–1
9.10
5.73
5.63
5.07
12.81
5.10
2.19
0.00
3.14
0.00
2.11
0.00
4.39
0.00
2.69
0.00
2.46
0.00
4.26
0.00
4.26
0.00
2.47
0.00
4.28
0.00
2.29
0.00
2.14
0.00
1.86
0.00
Std.
10.70
6.74
6.62
5.96
15.06
6.00
2.57
0.00
3.69
0.00
2.48
0.00
5.16
0.00
3.17
0.00
2.89
0.00
5.01
0.00
5.00
0.00
2.90
0.00
5.03
0.00
2.69
0.00
2.52
0.00
2.19
0.00
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2-54
Revision 4