M1AFS600-PQ208 Datasheet, PDF (40/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Device Architecture
Clock Source
Input LVDS/LVPECL Macro
PADN
Y
PADP
INBUF² Macro
PAD
Y
Clock Conditioning
CLKA
GLA
EXTFB
LOCK
POWERDOWN
OADIVRST
OADIVHALF
OADIV[4:0]
OAMUX[2:0]
DLYGLA[4:0]
OBDIV[4:0]
OBMUX[2:0]
DLYYB[4:0]
DLYGLB[4:0]
OCDIV[4:0]
OCMUX[2:0]
DLYYC[4:0]
DLYGLC[4:0]
FINDIV[6:0]
FBDIV[6:0]
FBDLY[4:0]
FBSEL[1:0]
XDLYSEL
VCOSEL[2:0]
GLB
YB
GLC
YC
Output
GLA
or
GLA and (GLB or YB)
or
GLA and (GLC or YC)
or
GLA and (GLB or YB) and
(GLC or YC)
Notes:
1. Visit the Microsemi SoC Products Group website for application notes concerning dynamic PLL reconfiguration. Refer to
the "PLL Macro" section on page 2-29 for signal descriptions.
2. Many specific INBUF macros support the wide variety of single-ended and differential I/O standards for the Fusion family.
3. Refer to the IGLOO, ProASIC3, SmartFusion and Fusion Macro Library Guide for more information.
Figure 2-19 • Fusion CCC Options: Global Buffers with the PLL Macro
Table 2-11 • Available Selections of I/O Standards within CLKBUF and CLKBUF_LVDS/LVPECL Macros
CLKBUF Macros
CLKBUF_LVCMOS5
CLKBUF_LVCMOS33¹
CLKBUF_LVCMOS18
CLKBUF_LVCMOS15
CLKBUF_PCI
CLKBUF_LVDS²
CLKBUF_LVPECL
Notes:
1. This is the default macro. For more details, refer to the IGLOO, ProASIC3, SmartFusion and Fusion Macro Library
Guide.
2. The B-LVDS and M-LVDS standards are supported with CLKBUF_LVDS.
2-24
Revision 4