M1AFS600-PQ208 Datasheet, PDF (188/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Device Architecture
Detailed I/O DC Characteristics
Table 2-95 • Input Capacitance
Symbol
Definition
Conditions
Min.
Max.
Units
C_IN
C_INCLK
Input capacitance
Input capacitance on the clock pin
VIN = 0, f = 1.0 MHz
VIN = 0, f = 1.0 MHz
8
pF
8
pF
Table 2-96 • I/O Output Buffer Maximum Resistances ¹
Standard
Drive Strength
R_{P(oUhLLm-DsO) W2 N}
R(o_{PhUmLLs-U) 3P}
Applicable to Pro I/O Banks
3.3 V LVTTL / 3.3 V LVCMOS
4 mA
100
300
8 mA
50
150
12 mA
25
75
16 mA
17
50
24 mA
11
33
2.5 V LVCMOS
4 mA
100
200
8 mA
50
100
12 mA
25
50
16 mA
20
40
24 mA
11
22
1.8 V LVCMOS
2 mA
200
225
4 mA
100
112
6 mA
50
56
8 mA
50
56
12 mA
20
22
16 mA
20
22
1.5 V LVCMOS
2 mA
200
224
4 mA
100
112
6 mA
67
75
8 mA
33
37
12 mA
33
37
3.3 V PCI/PCI-X
Per PCI/PCI-X specification
25
75
3.3 V GTL
20 mA
11
–
2.5 V GTL
20 mA
14
–
3.3 V GTL+
35 mA
12
–
2.5 V GTL+
33 mA
15
–
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend
on VCC, drive strength selection, temperature, and process. For board design considerations and detailed output buffer
resistances, use the corresponding IBIS models located on the Microsemi SoC Products Group website:
http://www.microsemi.com/soc/techdocs/models/ibis.html.
2. R_{(PULL-DOWN-MAX)} = VOLspec / I_OLspec
3. R_{(PULL-UP-MAX)} = (VCCImax – VOHspec) / IOHspec
2-172
Revision 4