M1AFS600-PQ208 Datasheet, PDF (43/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Fusion Family of Mixed Signal FPGAs
Global Input Selections
Each global buffer, as well as the PLL reference clock, can be driven from one of the following (Figure 2-
22):
• 3 dedicated single-ended I/Os using a hardwired connection
• 2 dedicated differential I/Os using a hardwired connection
• The FPGA core
Each shaded box represents an
input buffer called out by the
appropriate name: INBUF or
INBUF_LVDS/LVPECL.
Sample Pin Names
GAA0¹
To Core
GAA1¹
+
Source for CCC
(CLKA or CLKB or CLKC)
GAA2¹
+
(froRmouFtPedGCAlcoocrke)²
GAA[0:2]: GA represents global in the northwest corner
of the device. A[0:2]: designates specific A clock source.
Notes:
1. Represents the global input pins. Globals have direct access to the clock conditioning block and are not
routed via the FPGA fabric. Refer to the "User I/O Naming Convention" section on page 2-161 for more
information.
2. Instantiate the routed clock source input as follows:
a) Connect the output of a logic element to the clock input of the PLL, CLKDLY, or CLKINT macro.
b) Do not place a clock source I/O (INBUF or INBUF_LVPECL/LVDS) in a relevant global pin location.
3. LVDS-based clock sources are available in the east and west banks on all Fusion devices.
Figure 2-22 • Clock Input Sources Including CLKBUF, CLKBUF_LVDS/LVPECL, and CLKINT
Revision 4
2- 27