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M1AFS600-PQ208 Datasheet, PDF (180/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs
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Device Architecture
tPY
tDIN
tPYS
PAD
DQ
Y
DIN
CLK
To Array
tPY = MAX(tPY (R), tPY (F))
tPYs = MAX(tPYS (R), tPYS (F))
tDIN = MAX(tDIN (R), tDIN (F))
I/O interface
VIH
PAD
Vtrip
Vtrip
VIL
VCC
Y
GND
50%
tPY
(R)
tPYS
(R)
DIN
GND
50%
tDIN
(R)
50%
tPY
(F)
tPYS
(F)
VCC
tDIN
(F)
Figure 2-116 • Input Buffer Timing Model and Delays (example)
50%
2-164
Revision 4
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