M1AFS600-PQ208 Datasheet, PDF (125/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Fusion Family of Mixed Signal FPGAs
Table 2-40 • Analog MUX Channels (continued)
Analog MUX Channel
Signal
16
AV5
17
AC5
18
AT5
19
AV6
20
AC6
21
AT6
22
AV7
23
AC7
24
AT7
25
AV8
26
AC8
27
AT8
28
AV9
29
AC9
30
AT9
31
Internal temperature
monitor
Analog Quad Number
Analog Quad 5
Analog Quad 6
Analog Quad 7
Analog Quad 8
Analog Quad 9
The ADC can be powered down independently of the FPGA core, as an additional control or for power-
saving considerations, via the PWRDWN pin of the Analog Block. The PWRDWN pin controls only the
comparators in the ADC.
ADC Modes
The Fusion ADC can be configured to operate in 8-, 10-, or 12-bit modes, power-down after conversion,
and dynamic calibration. This is controlled by MODE[3:0], as defined in Table 2-41 on page 2-109.
The output of the ADC is the RESULT[11:0] signal. In 8-bit mode, the Most Significant 8 Bits
RESULT[11:4] are used as the ADC value and the Least Significant 4 Bits RESULT[3:0] are logical '0's.
In 10-bit mode, RESULT[11:2] are used the ADC value and RESULT[1:0] are logical 0s.
Table 2-41 • Mode Bits Function
Name
Bits
Function
MODE
3 0 – Internal calibration after every conversion; two ADCCLK cycles are used
after the conversion.
1 – No calibration after every conversion
MODE
2 0 – Power-down after conversion
1 – No Power-down after conversion
MODE
1:0 00 – 10-bit
01 – 12-bit
10 – 8-bit
11 – Unused
Integrated Voltage Reference
The Fusion device has an integrated on-chip 2.56 V reference voltage for the ADC. The value of this
reference voltage was chosen to make the prescaling and postscaling factors for the prescaler blocks
change in a binary fashion. However, if desired, an external reference voltage of up to 3.3 V can be
Revision 4
2- 109