M1AFS600-PQ208 Datasheet, PDF (168/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Device Architecture
Selectable Skew between Output Buffer Enable/Disable Time
The configurable skew block is used to delay the output buffer assertion (enable) without affecting
deassertion (disable) time.
Output Enable ENABLE (IN)
(from FPGA core)
Skew Circuit
MUX
ENABLE (OUT)
I/O Output
Buffers
Skew Select
Figure 2-107 • Block Diagram of Output Enable Path
ENABLE (IN)
ENABLE (OUT)
Less than
0.1 ns
Less than
0.1 ns
Figure 2-108 • Timing Diagram (option1: bypasses skew circuit)
ENABLE (IN)
ENABLE (OUT)
1.2 ns
(typical)
Less than
0.1 ns
Figure 2-109 • Timing Diagram (option 2: enables skew circuit)
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Revision 4