M1AFS600-PQ208 Datasheet, PDF (31/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Fusion Family of Mixed Signal FPGAs
Clock Aggregation
Clock aggregation allows for multi-spine clock domains. A MUX tree provides the necessary flexibility to
allow long lines or I/Os to access domains of one, two, or four global spines. Signal access to the clock
aggregation system is achieved through long-line resources in the central rib, and also through local
resources in the north and south ribs, allowing I/Os to feed directly into the clock system. As Figure 2-14
indicates, this access system is contiguous.
There is no break in the middle of the chip for north and south I/O VersaNet access. This is different from
the quadrant clocks, located in these ribs, which only reach the middle of the rib. Refer to the Using
Global Resources in Actel Fusion Devices application note.
Global Spine
Global Rib
Global Driver and MUX
Tree Node MUX
I/O Access
Internal Signal Access
Global Signal Access
Figure 2-14 • Clock Aggregation Tree Architecture
I/O Tiles
Revision 4
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