M1AFS600-PQ208 Datasheet, PDF (78/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Device Architecture
DINA and DINB
These are the input data signals, and they are nine bits wide. Not all nine bits are valid in all
configurations. When a data width less than nine is specified, unused high-order signals must be
grounded (Table 2-29).
DOUTA and DOUTB
These are the nine-bit output data signals. Not all nine bits are valid in all configurations. As with DINA
and DINB, high-order bits may not be used (Table 2-29). The output data on unused pins is undefined.
Table 2-29 • Unused/Used Input and Output Data Pins for Various Supported Bus Widths
DINx/DOUTx
D×W
Unused
Used
4k×1
[8:1]
[0]
2k×2
[8:2]
[1:0]
1k×4
[8:4]
[3:0]
512×9
None
[8:0]
Note: The "x" in DINx and DOUTx implies A or B.
2-62
Revision 4