M1AFS600-PQ208 Datasheet, PDF (49/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Fusion Family of Mixed Signal FPGAs
Real-Time Counter System
The RTC system enables Fusion devices to support standby and sleep modes of operation to reduce
power consumption in many applications.
• Sleep mode, typical 10 µA
• Standby mode (RTC running), typical 3 mA with 20 MHz
The RTC system is composed of five cores:
• RTC sub-block inside Analog Block (AB)
• Voltage Regulator and Power System Monitor (VRPSM)
• Crystal oscillator (XTLOSC); refer to the "Crystal Oscillator" section in the Fusion Clock
Resources chapter of the Fusion FPGA Fabric User’s Guide for more detail.
• Crystal clock; does not require instantiation in RTL
• 1.5 V voltage regulator; does not require instantiation in RTL
All cores are powered by 3.3 V supplies, so the RTC system is operational without a 1.5 V supply during
standby mode. Figure 2-27 shows their connection.
AB
Real-Time Counter
RTCMATCH
RTCPSMMATCH
RTCCLK
RTCXTLSEL RTCXTLMODE[1:0]
XTLOSC
SELMODE
RTC_MODE[1:0]
MODE[1:0]
FPGA_EN¹
CLKOUT
XTL
Crystal Clock
XTL¹
XTAL1 XTAL2
VRPSM
VRPU
VRINITSTATE
RTCPSMMATCH
FPGAGOOD
PUCORE
VREN¹
PUB
TRST¹
1.5 Voltage Regulator
PTBASE¹
VREN¹
PTEM¹
3.3 V
External
Pass
Transistor
2N2222
1.5 V
Can Be Route
to PLL
Power-Up/-Down
Toggle Control
Switch
External Pin
Internal Pin
Cores do not require any
RTL instantiation
Cores require RTL instantiation²
Sub-block in cores does not
require additional RTL instantiation
Notes:
1. Signals are hardwired internally and do not exist in the macro core.
2. User is only required to instantiate the VRPSM macro if the user wishes to specify PUPO behavior of the voltage regulator
to be different from the default, or employ user logic to shut the voltage regulator off.
Figure 2-27 • Real-Time Counter System (not all the signals are shown for the AB macro)
Revision 4
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