M1AFS600-PQ208 Datasheet, PDF (38/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Device Architecture
1.00E-0.3
RC Time Constant Values vs. Frequency
1.00E-0.4
1.00E-0.5
1.00E-0.6
1.00E-0.7
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
Frequency (MHz)
Figure 2-18 • Crystal Oscillator: RC Time Constant Values vs. Frequency (typical)
Table 2-10 • XTLOSC Signals Descriptions
Signal Name
Width Direction
Function
XTL_EN*
1
Enables the crystal. Active high.
XTL_MODE*
2
Settings for the crystal clock for different frequency.
Value
Modes
Frequency Range
b'00
RC network
32 KHz to 4 MHz
b'01
Low gain
32 to 200 KHz
b'10
Medium gain
0.20 to 2.0 MHz
b'11
High gain
2.0 to 20.0 MHz
SELMODE
1
IN
Selects the source of XTL_MODE and also enables the
XTL_EN. Connect from RTCXTLSEL from AB.
0
For normal operation or sleep mode, XTL_EN
depends on FPGA_EN, XTL_MODE depends on
MODE
1
For Standby mode, XTL_EN is enabled,
XTL_MODE depends on RTC_MODE
RTC_MODE[1:0] 2
IN
Settings for the crystal clock for different frequency ranges.
XTL_MODE uses RTC_MODE when SELMODE is '1'.
MODE[1:0]
2
IN
Settings for the crystal clock for different frequency ranges.
XTL_MODE uses MODE when SELMODE is '0'. In Standby,
MODE inputs will be 0's.
FPGA_EN*
1
IN
0 when 1.5 V is not present for VCC 1 when 1.5 V is present
for VCC
XTL
1
IN Crystal Clock source
CLKOUT
1
OUT Crystal Clock output
Note: *Internal signal—does not exist in macro.
2-22
Revision 4