M1AFS600-PQ208 Datasheet, PDF (189/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs

Fusion Family of Mixed Signal FPGAs
Table 2-96 • I/O Output Buffer Maximum Resistances ¹ (continued)
Standard
Drive Strength
R_{P(oUhLLm-DsO) W2 N}
R(o_{PhUmLLs-U) 3P}
HSTL (I)
8 mA
50
50
HSTL (II)
15 mA
25
25
SSTL2 (I)
17 mA
27
31
SSTL2 (II)
21 mA
13
15
SSTL3 (I)
16 mA
44
69
SSTL3 (II)
24 mA
18
32
Applicable to Advanced I/O Banks
3.3 V LVTTL / 3.3 V LVCMOS
2 mA
100
300
4 mA
100
300
6 mA
50
150
8 mA
50
150
12 mA
25
75
16 mA
17
50
24 mA
11
33
2.5 V LVCMOS
2 mA
100
200
4 mA
100
200
6 mA
50
100
8 mA
50
100
12 mA
25
50
16 mA
20
40
24 mA
11
22
1.8 V LVCMOS
2 mA
200
225
4 mA
100
112
6 mA
50
56
8 mA
50
56
12 mA
20
22
16 mA
20
22
1.5 V LVCMOS
2 mA
200
224
4 mA
100
112
6 mA
67
75
8 mA
33
37
12 mA
33
37
3.3 V PCI/PCI-X
Per PCI/PCI-X specification
25
75
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend
on VCC, drive strength selection, temperature, and process. For board design considerations and detailed output buffer
resistances, use the corresponding IBIS models located on the Microsemi SoC Products Group website:
http://www.microsemi.com/soc/techdocs/models/ibis.html.
2. R_{(PULL-DOWN-MAX)} = VOLspec / I_OLspec
3. R_{(PULL-UP-MAX)} = (VCCImax – VOHspec) / IOHspec
Revision 4
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